Efficient CTL* model checking for analysis of rainbow designs

On-the-Fly Model Checking of RCTL Formulas

The specification language RCTL, an extension of CTL, is defined by adding the power of regular expressions to CTL. In addition to being a more expressive and natural hardware specification language than CTL, a large family ofRCTL formulas can be verified on-the-fly (during symbolic reachability analysis). On-the-fly model checking, as a powerful verification paradigm, is especially efficient w...

Real-Time Veri cation of Statemate Designs

This paper presents an approach towards real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control units. These embedded control units are usually contained in industrial products and often implement concurrent systems. In our approach designs including all timing information are translated into untimed Kripke Structures which are optimized and the...

Efficient Symbolic Model Checking using Partitioned-OBDDs

This paper presents an efficient method to avoid memory explosion in symbolic model checking through the use of Partitioned-OBDDs (POBDDs). The partitioned approach requires only one partition to be in memory at any time and allows for differing variable orders to be used in the partitions. We present new algorithms for checking invariants and for model checking CTL formulas expressible as leas...

Real-Time Verification of Statemate Designs

This paper presents a toolset for real-time veriication of Statemate 1 designs. Statemate is a widely used design tool for embedded control applications. In our approach designs including all timing information are translated into untimed nite state machines (FSMs) which are veriied by symbolic model-checking. Real-time requirements are expressed by TCTL formulae interpreted over discrete time....

Model Checking CTL[DC] properties of SMV, Verilog and Esterel Designs